The formation of closely-spaced integrated circuits on the same silicon wafer is well-known, as is technology for conductive interconnection of such circuits. Traditional interconnection techniques use patterned wire metallurgy to form desired wiring levels. In VLSI devices, metal patterns are multi-layered and separated by layers of insulating material. Interconnection between different levels of metal wiring patterns is made by contact holes (or vias), which are etched through the layer of insulating material and filled with metallization to form stud via connections.
As described in U.S. Pat. No. 4,789,648 to Chow et al., which is assigned to the same assignee as the present application, patterned conductive lines may be formed simultaneously with stud via connections through an insulating layer to underlying metallization in multilevel VLSI chips. FIG. 1 shows a semiconductor structure 10 in which a first insulating layer 15 is deposited over a patterned metallization level 20 to which contact is desired. Contact holes or vias 25, which will then be used to form a stud via connection, are defined by photolithography aria in a first mask. layer 30, such as an etch stop material or photoresist, covering first insulating layer 15. A second insulating layer 115 is deposited onto first mask layer 30 followed by a second mask layer (not shown), which may be a photoresist or etch stop material, on second insulating layer 115. Second insulating layer 115 is etched by photolithography to first mask layer 30 to define desired wiring lines or grooves 40 and 50, some of which are in alignment with the previously formed contact holes 25. Alignment is facilitated by standard alignment means. Where contact holes 25 are exposed, the etching is continued into the first layer of insulation 15 to uncover underlying substrate metallization level 20. Where no contact hole is needed, etching stops on first mask layer 30, and second mask layer (not shown) is removed. Lines 40 and 50 and contact holes 25 are then overfilled with metallization, and the excess metallization is removed by etching or chemical mechanical polishing techniques. Device 10 having metallization lines 140 and stud via connections 130 is thereby formed. The etch and mask sequences and subsequent metal deposition and planarization techniques disclosed above are generally known as damascene techniques when one mask is used or dual damascene techniques when two masks are used.
In an alternative dual damascene embodiment (not shown), second insulating layer 115 is not deposited onto first mask layer 30. Instead, a second mask layer, comprising a photoresist or an etch stop material, is placed directly on first mask layer 30. where no contact hole is exposed, lines 40 and 50 are etched through second mask layer, underlying first mask layer 30, and about half way through first insulating layer 15. Contact holes 25 are defined through first insulating layer 15 where line 40 is aligned with a previously etched contact opening. Both masks are then removed, and the process continues as above with the deposition of a metal into the lines and contact holes.
In a multi-level device in which each level contains various conductive elements. inadvertent contact between levels can lead to electrical shorts and failure of the semiconductor device. For example, in a given device, some of the conductive metallization elements on a lower level are designed to contact conductive metallization elements on an adjacent upper level, while other level conductive metallization elements perform different functions and must remain isolated from upper level elements which happen to be situated immediately above them.
As used below, especially in the dual damascene structures described herein, the term "line image" refers to the openings 40 and 50 defined in the second mask layer overlying first mask layer 30, prior to translation through first mask layer 30 and into first insulating layer 15. "Lines" or "grooves" refer to the openings underlying the line images 50 that are etched through first mask layer 30 and into first insulating layer 15 and subsequently filled with metal to form metallization lines or conductive metallization elements. The term "contact opening" refers to the opening initially etched into first mask layer 30 which may be subsequently filled with a second mask layer prior to line image formation. The term "contact hole image" or "via image" refers to the opening defined where the line image overlaps or is aligned with the contact opening. The term "contact hole" is the opening underlying the line image/contact opening overlap and translated through first insulating layer 15 to substrate metallization 20. The contact holes are then filled with metal and planarized to form stud via connections. A "space" is the material that laterally separates adjacent metal lines or line images.
FIG. 2 is a top plan view showing a dual damascene structure having a line image/space/line image combination where the line images are defined photolithographically and have a minimum image size, M, for five different cases. In the first case, shown in Section A, the line image 40 is perfectly aligned to the underlying contact opening 100a, and the final contact hole image size 60a has dimensions, M.times.M. However, perfect alignment is generally not attained due to a bias of .DELTA. and tolerances across the wafer that exist in creating both the line image 40 and contact opening 100a. Section B shows a worst case alignment in which the overlay of the line image 40 over the contact opening 100b is half the minimum image size or M/2, as illustrated in the final contact hole image 60b. For example, for a 1.mu..times.1.mu. contact opening 100b, a worst case overlay of about 1/2.mu. across the entire wafer would result. The worst case alignment of Section B is further illustrated in FIG. 3 showing a cross-sectional view of the standard dual damascene multiple resist structure 10 taken along line B--B. A first resist 30, used for defining the contact hole 100b, underlies the second resist 35 used for line image 40 and 50 definition. As shown, misalignment of the resist images subtracts from the final size of the contact hole image 60b from M to M/2.
In order to avoid the above-mentioned problem and to ensure maximum contact hole size, the contact opening 100 in first resist 30 is initially made larger, up to about M/2 in both directions along the X-axis to form a contact opening 100 having the dimensions 2M.times.M. If the contact opening 100c is perfectly aligned with line image 40. the top view shown in Section C of FIG. 2 would be obtained. However, in a worst case misalignment where the overlay is M/2, as seen in Section D, the 2M contact opening 100d simply overlaps an adjoining space 80. Maximum overlap of dimension M is thus achieved between the line image 40 and the contact opening 100d, and the contact hole image 60d has a final size of M.times.M.
However, in practice, there are size variations in the contact hole images and line images formed in the wafer due to biases and tolerances across the wafer. If either the line image 40 or the contact hole image 60 size increases beyond the minimum image size M due to a bias .DELTA., then an unwanted overlap occurs, and hence unwanted contact with the underlying substrate metallization is made when the contact hole image 70 is later translated to the underlying insulator. This is shown in Section E of FIG. 2 and illustrated by contact hole images 60e and 70. For example, if there are variations, due to a bias (.DELTA.) of 0.1.mu., in the width of line images 40 and 50 having the dimensions of 1.mu..times.100 .mu., where M=1.mu., then in some locations of the wafer, the line may have a width of 1.1.mu., and in other locations, a width of 0.9.mu.. If an underlying contact opening 100e having the dimensions 2M.times.M is misaligned with line image 40 having a width of 1.1.mu., a worst case overlay of M/2 may occur such that the contact opening 100e also underlies a small. sublithographic line image area 70 in which contact to the substrate metallization is not wanted. Thus, when the contact hole image 70 is translated into the insulating layer and filled with a metal, undesired contact with the underlying substrate metallization occurs. The term "sublithographic" as used herein refers to an opening that is very much smaller than an opening formed using standard photolithographic patterning techniques, typically about 5% or less but may be as great as 10%.
The unwanted sublithographic contact described above is further illustrated in FIG. 4, which is a standard dual damascene structure 10 showing a cross-section of FIG. 2. Section E, taken along line E--E. Contact opening 100e has a width of 2M. Due to tolerances and bias factors, unwanted overlap 70 exists between line image 50 and contact opening 100e. As stated above, subsequent translation of the sublithographic contact hole image 70 through the underlying insulator 15 to device metallization within the substrate will result in the creation of not only contact holes at points of desired contact, but also very small contact holes, referred to herein as sublithographic, (in the areas of unwanted overlap or contact hole image 70) in which contact to the substrate metallization is not desired. Circuit shorting and failure will then occur when the resulting contact hole is filled with metal. Thus, a method is needed to fill the undesirable sublithographic contact hole images 70 or the sublithographic contact holes that are translated through the insulator 15 prior to metal deposition.
A conventional method for eliminating sublithographic surface defects in the insulating layer overlying a metallization level includes depositing a second insulating film over the first insulator to fill the defects followed by chemical mechanical polishing to planarize the surface. However, if in addition to the undesired sublithographic surface defects, there are contact holes etched through the first insulator that must remain open to underlying metallization, then the aforementioned method is not useful because the desired contact holes would also remain filled with the second insulating film material.
Cronin et al. in U.S. Pat. No. 5,118,382 disclose a method for filling unwanted undercuts in contact holes etched through an insulating layer. The undercut is filled with a layer of silicon dioxide or silicon nitride using chemical vapor deposition techniques. The deposited fill material conformally covers all surfaces including the underlying substrate surface exposed by the contact hole, the top surface of the insulating layer through which the contact hole is etched, the sidewalls of the contact hole, and the undercut. After sputter etching, a non-directional reactive ion plasma etch is used to remove the fill material from all the covered surfaces while leaving the undercut filled. Because the fill material is removed from the contact hole sidewalls and the substrate surface. contact to the substrate metallization through the contact hole is still possible. Thus, where the contact hole is unwanted and sublithographic. the method is ineffective because as well as reopening the larger, desired contact holes, the method also reopens the unwanted sublithographic contact hole to the underlying metallization.
A need therefore exists for a practical method that fills unwanted sublithographic contact hole defects formed in an insulating layer during dual damascene sequencing. Alternatively, a method is desired that prevents translation of such sublithographic contact holes into the insulator by filling the images prior to etching. A method is also desired that fills sublithographic openings formed during lithography or deposition of a single mask layer overlying an insulator. Such a method would diminish the amount of unwanted contact between metallization levels by eliminating stud via connections formed from sublithographic contact holes in the insulator. The method must permit contact holes to remain open where an opening is desired for subsequent metal deposition. In addition, self-alignment of the lines with the desired contact holes is necessary. Finally, the method should be efficient, inexpensive, and easy to practice without adding a complex number of process steps.